Within the field of the display apparatus, a liquid crystal display apparatus can have characteristics of thin profile and low power consumption. A liquid crystal display apparatus provided with a TFT substrate, having a switching element such as thin-film transistor (TFT) at each pixel, especially has a high contrast ratio and excellent response characteristics and exhibits high performance. Therefore, it is suitably used for, for example, a television receiver, a personal computer.
A plurality of gate lines (scan lines) and a plurality of source lines (signal lines) each crossing the respective gate lines with an insulation layer between are formed on the TFT substrate, and TFTs for switching the pixels are provided near the respective intersections where the gate lines cross source lines.
An exemplary example of a manufacturing method for a TFT substrate is described below.
First, a gate line is formed on a mother glass substrate, and a gate insulation film made of, for example, SiNx is formed so as to cover the upper sides of a gate line and a gate electrode, which is a part of the gate line. Further, a semiconductor film made of, for example, an amorphous silicon is formed by CVD.
Conventionally, the polycrystalline silicon is formed by treating an entire surface of the formed semiconductor film with heating or laser radiation, but recently, a method in which only a necessary portion is polycrystallized has been proposed (for example, JP 2011-029411 A). When a partial polycrystallization is required, the semiconductor film is subjected to a laser annealing process (hereinafter referred to as annealing process). The annealing process is a process in which a predetermined portion of the semiconductor film is irradiated with an energy beam to convert that portion into a polysilicon film. The polysilicon film corresponds to a channel region.
The annealing process is performed by using an annealing apparatus. For example, the annealing process is performed by irradiating a predetermined portion on a mother glass substrate, which is provided on a substrate stage, with a laser beam which is emitted by a laser oscillator provided in the annealing apparatus and guided through an optical system and a light guide path to pass through a mask stage on which a mask 50 (see below) with any aperture pattern is arranged. Alignment of the position of the mask 50 with respect to the mother glass substrate is performed on the basis of gate line pattern.
By performing an exposure using a mask and a development (hereinafter performing exposure and development is referred to as photolithography), a dry etching of the semiconductor film, and then, a removal of a resist, for example, the semiconductor film including a polysilicon region is patterned into an island shape.
Next, a source electrode and a drain electrode are formed by forming a conductive film (source film) made of, for example, Cu on the semiconductor film by sputtering, and performing a patterning by photolithography using a mask. Examples of an exposure apparatus for this process include an apparatus which projects an image of an original pattern formed in a photomask 60 (see below) onto a TFT substrate through a projection optical system.
Then, a passivation film, an interlayer insulation film, and a pixel electrode are formed accordingly.
FIG. 16 shows a schematic plan view of a TFT array region (TFT substrate region) 30 and a projected region on which a photomask 60 is projected on a mother glass substrate 70. FIG. 16 shows an example in which a plurality of TFT array regions 30 are cut out from the mother glass substrate 70.
The reference numeral 61 in FIG. 16 indicates an alignment mark formed on the photomask 60 to align the photomask 60 with which to perform a patterning of the above-described conductive film with the TFT array region 30. The alignment mark 61 is formed at the four corners of the photomask 60.
On a surface of the mother glass substrate 70, a plurality of alignment marks are formed outside the TFT array region 30 when performing a gate line patterning in the TFT array regions 30. Alignment is performed by reading an alignment mark on the mother glass substrate 70 and an alignment mark 61.
Namely, the position of the photomask 60 with respect to the TFT array region 30 will be adjusted by detecting a displacement between the alignment mark 61 and the alignment mark on the mother glass substrate 70.
It is necessary to retain the accuracy of the alignment high between the above-described annealed portion of the semiconductor film and the mask pattern for the conductive film including a source electrode, a drain electrode, a source line, and a drain connecting line.
As described above, after aligning the mask 50 with the mother glass substrate 70 on the basis of the gate lines and partially annealing the semiconductor film, the photomask 60 is aligned with the mother glass substrate 70 on the basis of the alignment mark 61 and the alignment mark on the mother glass substrate 70 and the conductive film is subjected to the patterning. However, since positions are not directly adjusted between the annealed portion and the photomask 60 for the conductive film (source film), it is difficult to attain a required positional accuracy.
FIG. 17 shows a schematic plan view of a positional relationship between a projected region on which the mask 50 is projected and a projected region on which the photomask 60 is projected.
As shown in FIG. 17, in an example of this annealing apparatus, a plurality of masks 50 are arranged in a column direction of the TFT array region 30, and simultaneously subjected to the annealing process, and then, the annealing apparatus is moved relatively in the row direction of the TFT array region 30, and annealing process is performed accordingly.
As shown in FIG. 17, the size of the mask 50 used for the annealing apparatus and the size of the photomask 60 used for the exposure apparatus are different. Specifically, while the size of the photomask 60 is approximately 1.5 m square, the size of the mask 50 for the laser annealing is approximately 30 cm square, and thus, their sizes are completely different, making it impossible to completely correct a displacement amount for each mask 50 generated due to the use of the smaller masks 50 than the photomask 60 when the alignment of the mask 60 is performed.
Further, a part of the uppermost mask 50 and a part of the lowermost masks 50 out of the plurality of masks 50 protrude from both long sides of the photomask 60, and it was impossible to adjust the arrangement of the photomask 60 in accordance with the arrangement of the mask 50.
JP 2012-119680 A discloses forming a pattern in a periphery of the photomask to calculate and correct a displacement of the mask (due to, for example, a thermal expansion or optical-path aberration), and then, correcting local position deviation according to a position deviation of a mask. Thereby, a displacement of a film of the bottom layer has been improved and a positional accuracy of a film overlaid on top of the film has been enhanced.
In JP 2012-119680 A, all the shapes of masks and the exposure apparatus to be used for all films are supposed to be same. In the case where a process is performed by using a mask which is completely different in size from a mask for exposure of a predetermined pattern, and a high positional accuracy between them is needed, it is considered difficult for the technique disclosed in No. 2012-119680 to actualize the required accuracy.